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www.lansdale.com page 1 of 24 issue 0 ml145162 60 mhz and 85 mhz universal programmable dual pll frequency synthesizers cmos legacy device: motorola mc145162 the ml145162 is a dual phase?ocked loop (pll) frequency synthesizer especially designed for ct? cordless phone applications worldwide. this frequency synthesizer is also for any product with a frequency operation at 60mhz or below. the device features fully programmable receive, transmit, reference, and auxiliary reference counters accessed through an mcu serial interface. this feature allows this device to operate in any ct? cordless phone application. the device consists of two independent phase detectors for transmit and receive loops. a common reference oscillator, driving two independent refer- ence frequency counters, provides independent reference frequencies for transmit and receive loops. the auxiliary reference counter allows the user to select an additional reference frequency for receive and transmit loops if required. ? operating voltage range: 2.5 to 5.5 v ? operating temperature range: t a = ?40 to +75? ? operating power consumption: 3.0 ma @ 2.5 v ? maximum operating frequency: 60 mhz @ 200 mv p?, v dd = 2.5 v ? three or four pins used for serial mcu interface builtin mcu clock output with frequency of reference oscillator 3/4 ? power saving mode controlled by mcu ? lock detect signal ? on?hip reference oscillator supports external crystals to 16.0 mhz ? reference frequency counter division range: 16 to 4095 ? auxiliary reference frequency counter division range: 16 to 16,383 ? transmit counter division range: 16 to 65,535 receive counter division range: 16 to 65,535 p dip 16 = ep pla s tic dip ca s e 64 8 sog 16 = -5p s og package ca s e 751b 16 1 16 1 cross reference/ordering information motorola p dip 16 mc145162p ml145162ep s og 16 MC145162D ml145162-5p lan s dale package note : lansdale lead free ( p b ) product, as it becomes available, will be identified by a part number prefix change from ml to ml e . pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 v dd txps/f tx f in ? txpd out ld f in ? rxpd out rxps/f rx enb d in ad in clk osc out osc in v ss mcuclk
www.lansdale.com page 2 of 24 issue 0 lansdale semiconductor, inc. ml145162 4 25 d c b a osc out osc in mcuclk ad in enb d in clk txps/f tx f in ? f in ? rxps/f rx 3/ 4 f r2 f r1 ld rxpd out txpd out 12?it programmable reference counter 12?it shift register mcu interface programming mode control control register tx phase detector 14?it programmable auxiliary reference counter 14?it shift register 16?it shift register 16?it shift register 16?it tx programmable counter 16?it rx programmable counter rx phase detector 7 8 5 2 1 3 4 13 11 14 9 15 16 10 transmit select receive select v dd = pin 12 v ss = pin 6 block diagram
www.lansdale.com page 3 of 24 issue 0 maximum ratings* (voltages referenced to v ss ) symbol rating value unit v dd dc supply voltage ?0.5 to + 6.0 v v in input voltage, all inputs ?0.5 to v dd + 0.5 v i in , i out dc current drain per pin 10 ma i dd , i ss dc current drain v dd or v ss pins 30 ma t stg storage temperature range ?65 to + 150 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin descriptions section. electrical characteristics (voltages referenced to v ss , t a = 25 c) guaranteed limit symbol characteristic v dd min max unit v dd power supply voltage range 2.5 5.5 v v ol output voltage 0 level (i out = 0) 2.5 5.5 0.1 0.1 v v oh (v in =v dd or 0) 1 level 2.5 5.5 2.45 5.45 v il input voltage 0 level (v out = 0.5 v or v dd 0.5 v) 2.5 5.5 0.75 1.65 v v ih 1 level 2.5 5.5 1.75 3.85 i oh output current (v out = 2.2 v) source (v out = 5.0 v) 2.5 5.5 ?0.18 ?0.55 ma i ol (v out = 0.3 v) sink (v out = 0.5 v) 2.5 5.5 0.18 0.55 i il input current osc in , f in ?, f in ? (v in = 0) 2.5 5.5 ?30 ?66 a ad in , clk, d in , enb 2.5 5.5 ?1.0 ?1.0 i ih (v in =v dd 0.5) osc in , f in ?, f in ? 2.5 5.5 30 66 ad in , clk, d in , enb 2.5 5.5 5.0 5.0 i oz three?tate leakage current (v out = 0 v or 5.5 v) 5.5 100 na c in input capacitance 8.0 pf c out output capacitance 8.0 pf i dd(stdby) standby current (all counters are in power?own mode with oscillator on) 2.5 5.5 0.3 1.5 ma i dd operating current ml145162: 200 mv p? input at f in ? and f in ? = 60 mhz 2.5 3.0 ma this device contains protection circuitry to guard against damage due to high static volt- ages or electric fields. however, precautions must be taken to avoid application of any voltage higher than maximum rated voltages to this high?mpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused pins must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. lansdale semiconductor, inc. ml145162
www.lansdale.com page 4 of 24 issue 0 lansdale semiconductor, inc. ml145162 switching characteristics (t a = 25 c, c l = 50 pf) figure guaranteed limit symbol characteristic figure no. v dd min max unit t tlh output rise time 1 2.5 5.5 200 100 ns t thl output fall time 1 2.5 5.5 200 100 ns t r , t f input rise and fall time osc in 2 2.5 5.5 5.0 4.0 s t w input pulse width clk and enb 3 2.5 5.5 80 60 ns f max input frequency osc in input = sine wave @ 200 mv p? f in ?, f in ? 2.5 ?5.5 2.5 ?5.5 16 60 mhz t st minimum start?p time 10 ms t su setup time data to clk enb to clk 5 2.5 5.5 100 200 ns t h hold time clk to data 5 3.0 5.0 80 40 ns t rec recovery time enb to clk 5 3.0 5.0 80 40 ns t su1 setup time enb to clk 4 2.5 ?5.5 80 ns t h1 hold time clk to enb 4 2.5 ?5.5 600 ns f phase detector frequency dc 12.5 khz f mcuclk output clock frequency mcuclk (osc in 3) dc 5.33 mhz
www.lansdale.com page 5 of 24 issue 0 switching waveforms t tlh any output 90% 10% t thl t r t f 90% 10% clk, osc in , f in ?, f in ? figure 1. figure 2. figure 3. figure 4. enb high during serial transfer enb, clk 50% t w clk first clk t h1 last clk t su1 v dd v ss v dd v ss ad in , d in clk enb 50% last clk t rec 50% previous data latched first clk t su 50% t su t h v dd v ss v dd v ss v dd v ss figure 5. enb low during serial transfer enb lansdale semiconductor, inc. ml145162
www.lansdale.com page 6 of 24 issue 0 lansdale semiconductor, inc. ml145162 pin descriptions input pins osc in /osc out reference oscillator input/output (pins 7, 8) these pins form a reference oscillator when connected to an external par- allel?esonant crystal. figure 6 shows the relationship of dif- ferent crystal frequencies and reference frequencies for cord- less phone applications in various countries. osc in may also serve as input for an externally generated reference signal which is typically ac coupled. mcuclk system clock (pin 5) this output pin provides a signal of the crystal frequency (osc out ) divided by 3 or 4 that is controlled by a bit in the control register. this signal can be a clock source for the mcu or other sys- tem clocks. adi n ,d in , clk, enb auxiliary data in, data in, clock, enable (pins 2, 3, 1, 4) these four pins provide an mcu serial interface for pro- gramming the reference counter, the transmit?hannel count- er, and the receive?hannel counter. they also provide various controls of the pll including the power saving mode and the programming format. txps/f tx , rxps/f rx transmit power save, receive power save (pins 13, 11) for a normal application, these output pins provide the status of the internal power saving mode operation. if the transmit?hannels counter circuitry is in power down mode, txps/f tx outputs a high state. if the receive?hannels counter circuitry is in power down mode, rxps/f rx is set high. these outputs can be applied for controlling the external power switch for the transmitter and the receiver to save mcu control pins. in the tx/rx channel counter test mode, the txps/f tx and rxps/f rx pins output the divided value of the transmit channel counter (f tx ) and the receive channel counter (f rx ), respec- tively. this test mode operation is controlled by the control register. details of the counter test mode are in the tx/rx channel counter test section of this data sheet. f in ?/f in ? transmit/receive counter inputs (pins 14, 9) f in ? and f in ? are inputs to the transmit and the receive counters, respectively. these signals are typically driven from the loop vco and ac coupled. the minimum input signal level is 200 mv p? @ 60.0 mhz. output pins txpd out /rxpd out transmit/receive phase detector outputs (pins 15, 10) these are three?tate outputs of the transmit and receive phase detectors for use as loop error signals (see figure 7 for phase detector output wave forms). phase detector gain isv dd /4 volts per radian. frequency f v > f r or f v leading: output = negative pulse. frequency f v < f r or f v lagging: output = positive pulse. frequency f v = f r and phase coincidence: output = high? impedance state. note: f r is the divided?own reference frequency at the phase detector input and f v is the divided?own vco frequen- cy at the phase detector input. ld lock detect (pin 16) the lock detect signal is associated with the transmit loop. the output at a high level indicates an out?f?ock condition (see figure 7 for the ld output wave form). power supply v dd positive power supply (pin 12) v dd is the most positive power supply potential ranging from 2.5 to 5.5 v with respect to v ss . v ss negative power supply (pin 6) v ss is the most negative supply potential and is usually con- nected to ground. m (14 bits) osc out osc in d c b a f r2 f r1 n (12 bits) 4 25 crystal n value f r1 b f r2 c 11.150 mhz 446 6.25 khz 1.0 khz 11.150 mhz 223 12.5 khz 10.240 mhz 512 5.0 khz 12.000 mhz 600 5.0 khz figure 6. reference frequencies for cordless phone applications of various countries
www.lansdale.com page 7 of 24 issue 0 mcu programming scheme the mcu programming scheme is defined in two formats controlled by the enb input. if the enable signal is high during the serial data transfer, control register/reference frequency programming is selected. if the enb is low, programming of the transmit and receive counters is selected. during program- ming of the transmit and receive counters, both ad in and d in pins can input the data to the transmit and receive counters. both counters data is clocked into the pll internal shift regis- ter at the leading edge of the clk signal. it is not necessary to reprogram the reference frequency counter/control register when using the enable signal to program the transmit/receive channels. in programming the control register/reference frequency scheme, the most significant bit (msb) of the programming word identifies whether the input data is the control word or the reference frequency data word. if the msb is 1, the input data is the control word (figure 8). also see figure 8 and table 1 for control register and bit function. if the msb is 0, the input data is the reference frequency (figure 9). the reference frequency data word is a 32?it word contain- ing the 12?it reference frequency data, the 14?it auxiliary reference frequency counter information, the reference fre- quency selection plus, the auxiliary reference frequency count- er enable bit (figure 9). if the aux ref enb bit is high, the 14?it auxiliary refer- ence frequency counter provides an additional phase reference frequency output for the loops. if aux ref enb bit is low, the auxiliary reference frequency counter is forced into power?own mode for current saving. (other power down modes are also provided through the control register per table 2 and figure 8.) at the falling edge of the enb signal, the data is stored in the registers. there are two interfacing schemes for the universal channel mode: the three?in and the four?in interfacing schemes. the three?in interfacing scheme is suited for use with the mcu spi (serial peripheral interface) (figure 10), while the four?in interfacing scheme is commonly used for general i/o port con- nection (figure 11). for the three?in interfacing scheme, the auxiliary data select bit is set to 0. all 32 bits of data, which define both the16?it transmit counter and the 16?it receive counter, latch into the pll internal register through the data in pins at the leading edge of clk. see figures 12 and 13. for the four?in interfacing scheme, the auxiliary data select bit is set to 1. in this scheme, the 16?it transmit counters data enters into the ad in pin at the same time as the 16?it receive counters data enters into the d in pin. this simultaneous entry of the transmit and receive counters causes the programming period of the four?in scheme to be half that of the three?in scheme (see figures 14 and 15). while programming tx/rx channel counter, the enb pin must be pulsed to provide falling edge to latch the shifted data after the rising edge of the last clock. maximum data transfer rate is 500 kbps. note 10 ms should be allowed for initial start?p time for the oscillator to allow all registers to clear and enable programming of new register values. lansdale semiconductor, inc. ml145162 v h = high voltage level. v l = low voltage level. *at this point, when both f r and f v are in phase, the output is forced to near mid supply. f r , reference (osc in reference counter) f v , feedback (f in ? tx counter or f in ? rx counter) txpd out or rxpd out v h v l v h v h v l high impedance * figure 7. phase detector/lock detector output waveforms ld note: the txpd out and rxpd out generate error pulses during out?f?ock conditions. when locked in phase and fre- quency, the output is high impedance and the voltage at that pin is determined by the low?ass filter capacitor.
www.lansdale.com page 8 of 24 issue 0 lansdale semiconductor, inc. ml145162 figure 8. programming format of the control register note: enb must be high during the serial transfer. enb control register identifier = 1 ref pd enable rxpd enable txpd enable 10 test bit aux data select control register data d in ref out msb lsb clk 3/ 4 table 1. control register function bits description test bit set to 1 for tx/rx channel counter test mode set to 0 for normal application aux data select set to 1 for both ad in and d in pins inputting the transmit 16?its data and receive 16?its data respectively. set to 0 for normal application interfacing with mcu serial peripheral interface. does not use ad in pin; tie ad in to v ss . ref out 3/ 4 if set to 1, ref out output frequency is equal to osc out 3. if set to 0, ref out output is osc out 4. txpd enable if set to 1, the transmit counter, transmit phase detector, and the associated circuitry is in power down mode. tx ps/f tx is set ?igh? rxpd enable if set to 1, the receive counter, receive phase detector, and the associated circuitry is in power down mode. rx ps/f rx is set ?igh? ref pd enable if set to 1, both 12?it and 14?it reference frequency counters are in power?own mode. table 2. control register power down bits function txpd enable rxpd enable ref pd enable tx?hannel counter rx?hannel counter reference frequency counter 0 0 0 0 0 1 power down 0 1 0 power down 0 1 1 power down power down 1 0 0 power down 1 0 1 power down power down 1 1 0 power down power down 1 1 1 power down power down power down
www.lansdale.com page 9 of 24 issue 0 f r1 s2 f r1 s1 aux ref enable 14?its aux ref freq data 12?its ref freq data reference frequency select aux reference frequency counter divide ratio reference frequency counter identifier = 0 reference frequency select 0 rx? select tx? select enb reference frequency counter divide ratio d in figure 9. programming format of the auxiliary/reference frequency counters note: enb must be high during the serial transfer. clk figure 10. mcu interface using spi enb clk d in mcu using serial peripheral interface port universal pll aux data bit = 0 figure 11. mcu interface using normal i/o ports with both d in and ad in for faster programming time d in enb clk ad in mcu using normal i/o port universal pll aux data bit = 1 lansdale semiconductor, inc. ml145162
www.lansdale.com page 10 of 24 issue 0 lansdale semiconductor, inc. ml145162 figure 12. programming format for control register (3?in interfacing scheme) aux data select = 0 enb control register identifier = 1 ref pd enable rxpd enable txpd enable 10 test bit aux data select control register data d in ref out msb lsb clk note: enb must be high during the serial transfer. 3/ 4 16?it rx counter divide ratio d in enb 16?it tx counter divide ratio figure 13. programming format for transmit and receive counters (3?in interfacing scheme) clk note: enb must be low during the serial transfer. last clock control register identifier = 1 ref pd enable rxpd enable txpd enable aux data select ref out 1 d in enb control register data a ux data select = 1 msb lsb figure 14. programming format for control register (4?in interfacing scheme) clk note: enb must be high during the serial transfer. 0 test bit 3/ 4
www.lansdale.com page 11 of 24 issue 0 reference frequency selection and programming figure 16 shows the bit function of the reference frequency programming word. the user can either select the ?ixed?ref- erence frequency for all channels accordingly or provide a spe- cific reference frequency for a particular channel by using two reference frequency counters (e.g., for an application in france, the base set transmit channel common fixed reference frequency is 6.25 khz or 12.5 khz). (see table 3 and figure 6 for reference frequencies for various countries.) however, transmit channels 6, 8, and 14 can be set to 25 khz, and chan- nel 8 reference frequency can be set to 50 khz. but this refer- ence frequency may not be applied to the receiving side; there- fore, the receiving side reference frequency must be generated by another reference frequency counter. the higher the refer- ence frequency, the better the phase noise performance and faster the lock time, but the pll consumes more current if both reference frequency counters are in operation. in general, the 12bit reference frequency counter plus the 4 and 25 module can offer all the reference frequencies for global ct? transmit and receive channel requirements. users can select their own reference frequency by introducing the additional 14?it auxiliary reference frequency counter. again, the 14?it auxiliary reference frequency counter can be shut down by the auxiliary reference enable bit in the refer- ence counter programming word by setting the bit to 0. at this state, the f r2 is automatically connected to point c (the ?5 block output), and f r1 can be connected to point a or b by setting the f r1 ?1 and f r1 ?2 bits in the reference counter program word. the 14?it auxiliary reference frequency count- er data will be in ?ont care?state. if the 14?it auxiliary reference frequency counter is enabled (auxiliary reference enable = 1), then f r2 is automatically con- nected to point d (14?it counter output), and f r1 can be selected to connect to point a, b, or c, depending on the bit setting of f r1 ?1 and f r1 ?2. table 4 and figure 16 describe the functions of the auxiliary reference enable bit and the f r1 ?1 and f r1 ?2 bits selection. lansdale semiconductor, inc. ml145162 ad in clk enb figure 15. programming format for transmit and receive counters (4?in interfacing scheme) 16?it tx counter divde ratio d in 16?it rx counter divide ratio note: enb must be low during the serial transfer. last clock table 3. global ct? reference frequency setting vs channel frequencies country channels frequency f r1 f r2 u.s.a. 46/49 mhz (10, 15, 25 channels) 5.0 khz france 26/41 mhz 6.25 khz/12.5 khz spain 31/41 mhz 5.0 khz australia 30/39 mhz 5.0 khz u.k. 1.7/47 mhz 6.25 khz 1.0 khz new zealand 1.7/34/40 mhz 6.25 khz 1.0 khz
www.lansdale.com page 12 of 24 issue 0 lansdale semiconductor, inc. ml145162 figure 16. reference frequency counter/selection programming mode 1 0 rx? select 1 0 tx? select d c b a osc out osc in f r2 f r1 ld rxpd out txpd out 12?it programmable reference counter tx phase detector maximum crystal frequency 16.0 mhz 14?it programmable auxiliary reference counter rx phase detector f r1 s2 f r1 s1 aux ref enable 14?its aux ref freq data 12?its ref freq data reference frequency select auxiliary reference frequency counter ref frequency counter identifier = 0 reference frequency select 0 rx? select tx? select enb reference frequency counter d in note: enb must be high during the serial transfer. clk 25 4 table 4. bit function and the reference frequency selection bit setting of the reference frequency counter programming word aux ref enable auxiliary reference frequency counter mode module select f r1 s1 f r1 s2 f r1 routing 0 14?it auxiliary reference frequency counter disable f r2 c 0 0 0 1 n/a f r1 a 1 0 f r1 b 1 1 n/a 1 14?it auxiliary reference frequency counter enable f r2 d 0 0 0 1 n/a f r1 a 1 0 f r1 b 1 1 f r1 c n/a = not applicable
www.lansdale.com page 13 of 24 issue 0 figure 17. txps/f tx and rxps/f rx outputs to control power switches of the transmitter and the receiver q q power switch for transmitter v dd universal dual pll rxps/f rx txps/f tx power supply tx power amp tx divider chain counter, phase detector tx power?own enable flag rx divider chain counter, phase detector rx power?own enable flag v dd to control the receiver power switch power saving operation this pll has a programmable power?aving scheme. the transmit and receive counters and the reference frequency counter can be powered down individually by setting the txpd enable, rxpd enable, and ref pd enable bits of the control register. the functions of the power down control bits are explained in table 2 and the programming format is in figure 8. the output pins txps/f tx and rxps/f rx output the status of the internal power saving setting. if the bit txpd enable is set ?igh?(transmit counter is set to power?own mode), then the txps/f tx pin will also output a ?igh?state. this txps/f tx out-put can control an external power switch to switch off the transmitter, as shown in figure 17. this scheme can be applied to the rxps/f rx output to control the receiver power saving operation as required. lansdale semiconductor, inc. ml145162
www.lansdale.com page 14 of 24 issue 0 lansdale semiconductor, inc. ml145162 f in ? 16?it rx programmable channels counter rxps rxps / f rx f rx 16?it tx programmable channels counter f in ? txps txps / f tx f tx if test bit is set to 1, the f tx and f rx are muxed out at pins txps/f tx and rxps/f rx , respectively, for rx/tx channel counter test. control register identifier = 1 ref pd enable rxpd enable txpd enable 10 test bit aux data select control register d in ref out figure 18. rf buffer sensitivity 3/ 4 tx/rx channel counter test in normal applications, the txps/f tx and the rxps/f rx out- put pins indicate the power saving mode status. however, the user can examine the tx and rx channel counter outputs by setting the test bit in the control register to 1. the final value of the transmit?hannel counter and the receive?hannel count- er multiplex out to txps/f tx and rxps/f rx respectively. the user can verify the divided?own output waveform associated with the rf input level in the pll circuitry implementation (figure 18).
www.lansdale.com page 15 of 24 issue 0 lansdale semiconductor, inc. ml145162 table 5. france ct? base set frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 6.25 khz) f in ? input frequency (mhz) [1st if = 10.7 mhz] rx counter value (ref. freq. = 6.25 khz) 1 26.4875 4238 30.7875 4926 2 26.4750 4236 30.7750 4924 3 26.4625 4234 30.7625 4922 4 26.4500 4232 30.7500 4920 5 26.4375 4230 30.7375 4918 6 26.4250 4228 30.7250 4916 7 26.4125 4226 30.7125 4914 8 26.4000 4224 30.7000 4912 9 26.3875 4222 30.6875 4910 10 26.3750 4220 30.6750 4908 11 26.3625 4218 30.6625 4906 12 26.3500 4216 30.6500 4904 13 26.3375 4214 30.6375 4902 14 26.3250 4212 30.6250 4900 15 26.3125 4210 30.6125 4898 table 6. france ct? handset frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 6.25 khz) f in ? input frequency (mhz) [1st if = 10.7 mhz] rx counter value (ref. freq. = 6.25 khz) 1 41.4875 6638 37.1875 5950 2 41.4750 6636 37.1750 5948 3 41.4625 6634 37.1625 5946 4 41.4500 6632 37.1500 5944 5 41.4375 6630 37.1375 5942 6 41.4250 6628 37.1250 5940 7 41.4125 6626 37.1125 5938 8 41.4000 6624 37.1000 5936 9 41.3875 6622 37.0875 5934 10 41.3750 6620 37.0750 5932 11 41.3625 6618 37.0625 5930 12 41.3500 6616 37.0500 5928 13 41.3375 6614 37.0375 5926 14 41.3250 6612 37.0250 5924 15 41.3125 6610 37.0125 5922
www.lansdale.com page 16 of 24 issue 0 lansdale semiconductor, inc. ml145162 table 7. spain ct? base set frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 5.00 khz) f in ? input frequency (mhz) [1st if = 10.695 mhz] rx counter value (ref. freq. = 5.00 khz) 1 31.0250 6205 29.2300 5846 2 31.0500 6210 29.2550 5851 3 31.0750 6215 29.2800 5856 4 31.1000 6220 29.3050 5861 5 31.1250 6225 29.3300 5866 6 31.1500 6230 29.3550 5871 7 31.1750 6235 29.3800 5876 8 31.2000 6240 29.4050 5881 9 31.2500 6250 29.4550 5891 10 31.2750 6255 29.4800 5896 11 31.3000 6260 29.5050 5901 12 31.3250 6265 29.5300 5906 table 8. spain ct? handset frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 5.00 khz) f in ? input frequency (mhz) [1st if = 10.7 mhz] rx counter value (ref. freq. = 5.00 khz) 1 39.9250 7985 20.3300 4066 2 39.9500 7990 20.3550 4071 3 39.9750 7995 20.3800 4076 4 40.0000 8000 20.4050 4081 5 40.0250 8005 20.4300 4086 6 40.0500 8010 20.4550 4091 7 40.0750 8015 20.4800 4096 8 40.1000 8020 20.5050 4101 9 40.1500 8030 20.5550 4111 10 40.1750 8035 20.5800 4116 11 40.2000 8040 20.6050 4121 12 40.2250 8045 20.6300 4126
www.lansdale.com page 17 of 24 issue 0 lansdale semiconductor, inc. ml145162 table 9. new zealand ct? base set frequency channel number tx channel frequency (mhz) tx counter value f in ? input frequency (mhz) [1st if = 10.7 mhz] rx counter value (ref. freq. = 6.25 khz) 1 1.7820 1782 29.7625 4762 2 1.7620 1762 29.7500 4760 3 1.7420 1742 29.7375 4758 4 1.7220 1722 29.7250 4756 5 1.7020 1702 29.7125 4754 6 34.3500 5496 29.7000 4752 7 34.3625 5498 29.6875 4750 8 34.3750 5500 29.6750 4748 9 34.3875 5502 29.6625 4746 10 34.4000 5504 29.6500 4744 table 10. new zealand ct? handset frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 6.25 khz) f in ? input frequency (mhz) rx counter value 1 40.4625 6474 2.2370 2237 2 40.4500 6472 2.2170 2217 3 40.4375 6470 2.1970 2197 4 40.4250 6468 2.1770 2177 5 40.4125 6466 2.1570 2157 6 40.4000 6464 23.6500 3784 7 40.3875 6462 23.6625 3786 8 40.3750 6460 23.6750 3788 9 40.3625 6458 23.6875 3790 10 40.3500 6456 23.7000 3792 ref freq = 1.0 khz ref freq = 6.25 khz ref freq = 455 khz ref freq = 10.7 khz ref freq = 1.0 khz ref freq = 6.25 khz
www.lansdale.com page 18 of 24 issue 0 lansdale semiconductor, inc. ml145162 table 11. australia ct? base set frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 5.00 khz) f in ? input frequency (mhz) [1st if = 10.695 mhz] rx counter value (ref. freq. = 5.00 khz) 1 30.0750 6015 29.0800 5816 2 30.1250 6025 29.1300 5826 3 30.1750 6035 29.1800 5836 4 30.2250 6045 29.2300 5846 5 30.2750 6055 29.2800 5856 6 30.1000 6020 29.1050 5821 7 30.1500 6030 29.1550 5831 8 30.2000 6040 29.2050 5841 9 30.2500 6050 29.2550 5851 10 30.3000 6060 29.3050 5861 table 12. australia ct? handset frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 5.00 khz) f in ? input frequency (mhz) [1st if = 10.7 mhz] rx counter value (ref. freq. = 5.00 khz) 1 39.7750 7955 19.3800 3876 2 39.8250 7965 19.4300 3886 3 39.8750 7975 19.4800 3896 4 39.9250 7985 19.5300 3906 5 39.9750 7995 19.5800 3916 6 39.8000 7960 19.4050 3881 7 39.8500 7970 19.4550 3891 8 39.9000 7980 19.5050 3901 9 39.9500 7990 19.5550 3911 10 40.0000 8000 19.6050 3921
www.lansdale.com page 19 of 24 issue 0 lansdale semiconductor, inc. ml145162 table 13. u.k. ct? base set frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 1.00 khz) f in ? input frequency (mhz) [1st if = 10.7 mhz] rx counter value (ref. freq. = 6.25 khz) 1 1.6420 1642 36.75625 5881 2 1.6620 1662 36.76875 5883 3 1.6820 1682 36.78125 5885 4 1.7020 1702 36.79375 5887 5 1.7220 1722 36.80625 5889 6 1.7420 1742 36.81875 5891 7 1.7620 1762 36.83125 5893 8 1.7820 1782 36.84375 5895 table 14. u.k. ct? handset frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 6.25 khz) f in ? input frequency (mhz) [1st if = 455 khz] rx counter value (ref. freq. = 1.00 khz) 1 47.45625 7593 2.097 2097 2 47.46875 7595 2.117 2117 3 47.48125 7597 2.137 2137 4 47.49375 7599 2.157 2157 5 47.50625 7601 2.177 2177 6 47.51875 7603 2.197 2197 7 47.53125 7605 2.217 2217 8 47.54375 7607 2.237 2237
www.lansdale.com page 20 of 24 issue 0 lansdale semiconductor, inc. ml145162 table 15. u.s.a. (10 channels) ct? base set frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 5.00 khz) f in ? input frequency (mhz) [1st if = 10.695 mhz] rx counter value (ref. freq. = 5.00 khz) 1 46.610 9322 38.975 7795 2 46.630 9326 38.150 7830 3 46.670 9334 38.165 7833 4 46.710 9342 39.075 7815 5 46.730 9346 39.180 7836 6 46.770 9354 39.135 7827 7 46.830 9366 39.195 7839 8 46.870 9374 39.235 7847 9 46.930 9386 39.295 7859 10 46.970 9394 39.275 7855 table 16. u.s.a. (10 channels) ct? handset frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 5.00 khz) f in ? input frequency (mhz) [1st if = 10.7 mhz] rx counter value (ref. freq. = 5.00 khz) 1 49.670 9934 35.915 7183 2 49.845 9969 35.935 7187 3 49.860 9972 35.975 7195 4 49.770 9954 36.015 7203 5 49.875 9975 36.035 7207 6 49.830 9966 36.075 7215 7 49.890 9978 36.135 7227 8 49.930 9986 36.175 7235 9 49.990 9998 36.235 7247 10 49.970 9994 36.275 7255
www.lansdale.com page 21 of 24 issue 0 lansdale semiconductor, inc. ml145162 table 17. u.s.a. (25 channels) ct? base set frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 5.00 khz) f in ? input frequency (mhz) [1st if = 10.7 mhz] rx counter value (ref. freq. = 5.00 khz) 1 43.72 8744 38.06 7612 2 43.74 8748 38.14 7628 3 43.82 8764 38.16 7632 4 43.84 8768 38.22 7644 5 43.92 8784 38.32 7664 6 43.96 8788 38.38 7676 7 44.12 8824 38.40 7680 8 44.16 8832 38.46 7692 9 44.18 8836 38.50 7700 10 44.20 8840 38.54 7708 11 44.32 8864 38.58 7716 12 44.36 8872 38.66 7732 13 44.40 8880 38.70 7740 14 44.46 8892 38.76 7752 15 44.48 8896 38.80 7760 16 46.61 9322 38.97 7794 17 46.63 9326 39.145 7829 18 46.67 9334 39.16 7832 19 46.71 9342 39.07 7814 20 46.73 9346 39.175 7835 21 46.77 9354 39.13 7826 22 46.83 9366 39.19 7838 23 46.87 9374 39.23 7846 24 46.93 9386 39.29 7858 25 46.97 9394 39.27 7854
www.lansdale.com page 22 of 24 issue 0 lansdale semiconductor, inc. ml145162 table 18. u.s.a. (25 channels) ct? handset frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 5.00 khz) f in ? input frequency (mhz) [1st if = 10.7 mhz] rx counter value (ref. freq. = 5.00 khz) 1 48.76 9752 33.02 6604 2 48.84 9768 33.04 6608 3 48.86 9772 33.12 6624 4 48.92 9748 33.14 6628 5 49.02 9804 33.22 6644 6 49.08 9816 33.26 6652 7 49.10 9820 33.42 6684 8 49.16 9832 33.46 6692 9 49.20 9840 33.48 6696 10 49.24 9848 33.50 6700 11 49.28 9856 33.62 6724 12 49.36 9872 33.66 6732 13 49.40 9880 33.70 6740 14 49.46 9892 33.76 6752 15 49.50 9900 33.78 6756 16 49.67 9934 33.91 7182 17 49.845 9969 33.93 7186 18 49.86 9972 33.97 7194 19 49.77 9954 36.01 7202 20 49.875 9975 36.03 7206 21 49.83 9966 36.07 7214 22 49.89 9978 36.13 7226 23 49.93 9986 36.17 7234 24 49.99 9998 36.23 7246 25 49.97 9994 36.27 7254 table 19. korea ct? base set frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 5.00 khz) f in ? input frequency (mhz) [1st if = 10.695 mhz] rx counter value (ref. freq. = 5.00 khz) 1 46.610 9322 38.975 7795 2 46.630 9326 38.150 7830 3 46.670 9334 38.165 7833 4 46.710 9342 39.075 7815 5 46.730 9346 39.180 7836 6 46.770 9354 39.135 7827 7 46.830 9366 39.195 7839 8 46.870 9374 39.235 7847 9 46.930 9386 39.295 7859 10 46.970 9394 39.275 7855 11 46.510 9302 39.000 7800 12 46.530 9306 39.015 7803 13 46.550 9310 39.030 7806 14 46.570 9314 39.045 7809 15 46.590 9318 39.060 7812
www.lansdale.com page 23 of 24 issue 0 lansdale semiconductor, inc. ml145162 table 20. korea ct? handset frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 5.00 khz) f in ? input frequency (mhz) [1st if = 10.7 mhz] rx counter value (ref. freq. = 5.00 khz) 1 49.670 9934 35.915 7183 2 49.845 9969 35.935 7187 3 49.860 9972 35.975 7195 4 49.770 9954 36.015 7203 5 49.875 9975 36.035 7207 6 49.830 9966 36.075 7215 7 49.890 9978 36.135 7227 8 49.930 9986 36.175 7235 9 49.990 9998 36.235 7247 10 49.970 9994 36.275 7255 11 49.695 9939 35.815 7163 12 49.710 9942 35.835 7167 13 49.725 9945 35.855 7171 14 49.740 9948 35.875 7175 15 49.755 9951 35.895 7179 table 21. china ct? base set frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 5.00 khz) f in ? input frequency (mhz) [1st if = 10.7 mhz] rx counter value (ref. freq. = 5.00 khz) 1 45.250 9050 37.550 7510 2 45.275 9055 37.575 7515 3 45.300 9060 37.600 7520 4 45.325 9065 37.625 7525 5 45.350 9070 37.650 7530 6 45.375 9075 37.675 7535 7 45.400 9080 37.700 7540 8 45.425 9085 37.725 7545 9 45.450 9090 37.750 7550 10 45.475 9095 37.775 7555 table 22. china ct? handset frequency channel number tx channel frequency (mhz) tx counter value (ref. freq. = 5.00 khz) f in ? input frequency (mhz) [1st if = 10.7 mhz] rx counter value (ref. freq. = 5.00 khz) 1 48.250 9650 34.550 6910 2 48.275 9655 34.575 6915 3 48.300 9660 34.600 6920 4 48.325 9665 34.625 6925 5 48.350 9670 34.650 6930 6 48.375 9675 34.675 6935 7 48.400 9680 34.700 6940 8 48.425 9685 34.725 6945 9 48.450 9690 34.750 6950 10 48.475 9695 34.775 6955
www.lansdale.com page 24 of 24 issue 0 outline dimensions p dip 16 = ep (ml145162ep) plastic dip case 648?8 note s : 1. dimen s ioning and tolerancing per an s i y14.5m, 19 8 2. 2. controlling dimen s ion: inch. 3 . dimen s ion l to center of lead s when formed parallel. 4. dimen s ion b doe s not include mold fla s h. 5. rounded corner s optional. ? b f c s h g d j l m 16 pl seating 18 9 16 k plane ? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 1 8 . 8 0 19.55 b 0.250 0.270 6. 3 5 6. 8 5 c 0.145 0.175 3 .69 4.44 d 0.015 0.021 0. 3 9 0.5 3 f 0.040 0.70 1.02 1.77 g 0.100 b s c 2.54 b s c h 0.050 b s c 1.27 b s c j 0.00 8 0.015 0.21 0. 38 k 0.110 0.1 3 0 2. 8 0 3 . 3 0 l 0.295 0. 3 05 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 sog 16 = -5p (ml145162-5p) sog package case 751b?5 note s : 1. dimen s ioning and tolerancing per an s i y14.5m, 19 8 2. 2. controlling dimen s ion: millimeter. 3 . dimen s ion s a and b do not include mold protru s ion. 4. maximum mold protru s ion 0.15 (0.006) per s ide. 5. dimen s ion d doe s not include dambar protru s ion. allowable dambar protru s ion s hall be 0.127 (0.005) total in exce ss of the d dimen s ion at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? ? m 0.25 (0.010) b s ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9. 8 0 10.00 0. 38 6 0. 3 9 3 b 3 . 8 0 4.00 0.150 0.157 c 1. 3 5 1.75 0.054 0.06 8 d 0. 3 5 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 b s c 0.050 b s c j 0.19 0.25 0.00 8 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5. 8 0 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 lansdale semiconductor, inc. ml145162 lansdale semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili- ty, function or design. lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. ?ypical parameters which may be provided in lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. all operating parameters, including ?ypicals must be validated for each customer application by the customers technical experts. lansdale semiconductor is a registered trademark of lansdale semiconductor, inc.

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